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Click here for this list in IEEE format.
Journal Publications 2020 “Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies”, in IEEE Transactions on Circuits and Systems I: Regular Papers “Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs”, in IEEE Transactions on Electron Devices “(Invited) Advanced Transistors for High Frequency Applications”, in ECS Transactions “A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/�s Slope and 1.2-GHz Chirp-Bandwidth”, in IEEE Journal of Solid - State Circuits 2019 “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “A 145GHz FMCW-Radar Transceiver in 28nm CMOS”, in Digest of technical papers - IEEE International Solid-State Circuits Conference “Integrated 140 GHz FMCW Radar for Vital Sign Monitoring and Gesture Recognition”, in Microwave journal (International ed.) “A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS”, in IEEE Journal of Solid-State Circuits “Multi-User Hybrid MIMO at 60 GHz Using 16-Antenna Transmitters”, in IEEE Transactions on Circuits and Systems I: Regular Papers 2018 “A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “Comparator hysteresis compensation for decision feedback equalisers”, in Electronics Letters “Comparator hysteresis compensation for decision feedback equalizers”, in Electronics Letters 2017 “A 21-dBm I/Q Digital Transmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology”, in IEEE Transactions on Microwave Theory and Techniques 2016 “A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends”, in IEEE Transactions on Microwave Theory and Techniques “A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs”, in IEEE Transactions on Electron Devices 2015 “A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers”, in IEEE Transactions on Circuits and Systems I: Regular Papers “A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “Design and Tuning of Coupled-LC mm-Wave Subharmonically Injection-Locked Oscillators”, in IEEE Transactions on Microwave Theory and Techniques “Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers”, in Journal of Signal Processing Systems 2014 “A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “A 4.1mW 3.5GS/s 6b time interleaved ADC in 40nm CMOS”, in IEEE Transactions on Microwave Theory and Techniques “A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS”, in IEEE Transactions on Circuits and Systems II: Express Briefs “A 79 GHz Phase-Modulated 4 GHz-BW CW Radar Transmitter in 28 nm CMOS”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS 2010 “A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “Reconfigurable single-chip radios”, in EDN 2009 “A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “A Fully Integrated 7.3 kV HBM ESD-Protected Tranformer-Based 4.5-6 GHz CMOS LNA”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS 2008 “A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS “Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS”, in IEEE Journal of Solid-State Circuits, November 2008 “A 52 GHz Phased-Array Receiver Front-End in 90nm Digital CMOS”, in IEEE Journal of Solid-State Circuits, December 2008 2007 “The potential of FinFETs for analog and RF circuit applications”, in IEEE Transactions on Circuits and Systems I: Regular Papers 2006 “Planar bulk MOSFETs versus FinFETs: an analog/RF perspective”, in IEEE Transactions on Electron Devices Conference Publications 2020 “A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/�s Slope and 1.2GHz Chirp Bandwidth”, in 2020 International Solid-State Circuits Conference “A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI”, in 2020 IEEE Custom Integrated Circuits Conference (CICC) “A 10.56Gbit/s, -27.8dB EVM Polar Transmitter at 60GHz in 28nm CMOS”, in 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) “A 28GHz Voltage-Combined Doherty Power Amplifier with a Compact Transformer-based Output Combiner in 22nm FD-SOI”, in 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) “A 28 GHz front-end module with T/R switch achieving 17.2 dBm Psat, 21.5% PAEmax and 3.2 dB NF in 22 nm FD-SOI for 5G communication”, in 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) 2019 “Systematic Design of On-Chip Matching Networks for D-band Circuits”, in 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) “Design of A D-band Transformer-Based Neutralized Class-AB Power Ampli?er in Silicon Technologies”, in 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) “A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter”, in 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 “A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE”, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference “Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications”, in 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019 “CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and Performance”, in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 “First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering”, in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 2018 “Semiconductor Technologies for next Generation Mobile Communications”, in 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 “Scaling CMOS beyond Si FinFET: An analog/RF perspective”, in 48th European Solid-State Device Research Conference, ESSDERC 2018 “A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS”, in 2018 Symposia on VLSI Technology and Circuits “3D technologies for analog/RF applications”, in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 “A 28-GHz Transceiver Front-End with T/R Switching Achieving 11.2-dBm OP1dB, 33.8% PAEmax and 4-dB NF in 22-nm FD-SOI for 5G Communication”, in SOI-3D-Subthreshold Microelectronics Unified Conference “PD-SOI: Enabling Adaptive RF Front-End Modules”, in SOI-3D-Subthreshold Microelectronics Unified Conference “A 23 GHz Low-Phase-Noise Transformer-Feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz”, in A 23 GHz Low-Phase-Noise Transformer-Feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz 2017 “In-Pixel Storage Techniques for CMOS Burst-Mode Ultra-High-Speed Imagers”, in International Image Sensor Workshop 2017 “A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier”, in 31st International Congress on High-Speed Imaging and Photonics “A 54-64.8 GHz Subharmonically Injection-Locked Frequency Synthesizer with Transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS”, in 43rd European Solid-State Circuits Conference “A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS”, in 2017 Symposium on VLSI Circuits “A fully-integrated method for RTN parameter extraction”, in Symposium on VLSI Technology 2016 “An Integrated Tunable Electrical-Balance Filter with >60dB Stopband Attenuation and 1.75-3.7GHz Stopband Tuning Range”, in European Microwave Week 2016 “A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers”, in IEEE International Solid-State Circuits Conference “Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs”, in Design-Process-Technology Co-optimization for Manufacturability X “A 4-Antenna-Path Beamforming Transceiver for 60GHz Multi-Gb/s Communication in 28nm CMOS”, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) “A 0.22mm2�CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise”, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) “A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL”, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) “A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS”, in 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 “60-GHz CMOS TX/RX chipset on organic packages with integrated phased-array antennas”, in 10th European Conference on Antennas and Propagation, EuCAP 2016 2015 “A 0.7-1.15GHz Complementary Common-Gate LNA in 0.18µm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD Protection”, in European Solid-State Circuits Conference “An Electrical-Balance Duplexer for In-Band Full-Duplex with <-85dBm In-Band Distortion at +10dBm TX-power”, in European Solid-State Circuits Conference “An Inductorless Electrical-Balance 360° Phase Shifter for 0.5-1.15GHz in 0.18µm CMOS”, in European Microwave Week “Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM”, in 2015 International Conference on IC Design & Technology (ICICDT) “Vertical device architecture for 5nm and beyond: device & circuit implications”, in 2015 Symposium on VLSI Technology and Circuits “Flicker noise upconversion mechanisms in K-band CMOS VCOs”, in Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian “A transmitter with 10b 128MS/s incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise”, in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers “A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS”, in Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian “A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS”, in European Solid-State Circuits Conference “A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS”, in European Solid-State Circuits Conference “A 79GHz binary phase-modulated continuous-wave radar transceiver with TX-to-RX spillover cancellation in 28nm CMOS”, in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers “An 80-GHz low noise amplifier resilient to the TX-spillover in phase-modulated continuous-wave radars”, in Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE “Modeling FinFET metal gate stack resistance for 14nm node and beyond”, in 2015 International Conference on IC Design & Technology (ICICDT) 2014 “A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS”, in 2014 IEEE International Solid-State Circuits Conference, ISSCC “Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies”, in 44th European Solid State Device Research Conference (ESSDERC) “Comparative Study of a Fully Differential Op Amp in FinFET and Planar Technologies”, in 10th Conference on PhD Research in Microelectronics and Electronics “Signal Processing Challenges for Emerging Digital Intensive and Digitally Assisted Transceivers with Deeply Scaled Technology”, in 2013 IEEE Workshop on Signal Processing Systems (SiPS 2013) “A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC”, in 40th European Solid-State Circuits Conference “A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS”, in 40th European Solid-State Circuit Conference “A Digitally Modulated 60GHz Polar Transmitter in 40nm CMOS”, in 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) “A 79GHz Phase-Modulated 4GHz-BW CW Radar TX in 28nm CMOS”, in 2014 IEEE International Solid-State Circuits Conference, ISSCC “A 5th subharmonic, inverter-based injection locked oscillator with 72–83GHz locking range”, in 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) “A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS”, in European Solid State Circuits Conference (ESSCIRC) “A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C”, in European Solid State Circuits Conference (ESSCIRC) “Design Technology co-optimization for N10”, in IEEE 2014 Custom Integrated Circuits Conference 2013 “A mm-Wave 40 nm CMOS Subharmonically Injection-Locked QVCO with Lock Detection”, in Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian “A 54-69.3 GHz Dual Band VCO with Differential Hybrid Coupler for Quadrature Generation”, in Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian “Frequency Enhancement of a 40-nm CMOS Static Frequency Divider by Negative Capacitance”, in Microwave Integrated Circuits Conference (EuMIC), 2013 European “CMOS low-power transceivers for 60GHz multi Gbit/s communications”, in the IEEE 2013 Custom Integrated Circuits Conference “A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication”, in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers “60GHz Transmitter Front-End in 40nm LP-CMOS with Improved Back-Off Efficiency”, in Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on “A 6.6 mW inductorless static 2:1 frequency divider operating up to 60 GHz in 28 nm CMOS”, in 2013 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems “Impact of multi-gate device architectures on digital and analog circuits and its implications on system-on-chip technologies”, in 2013 IEEE International Electron Devices Meeting 2012 “Analog baseband beamformer for use in a phased-array 60 GHz transmitter”, in 2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) “A 42mW Wideband Baseband Receiver Section with Beamforming Functionality for 60GHz Applications in 40nm Low-Power CMOS”, in 2012 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium “A CMOS IQ Digital Doherty Transmitter Using Modulated Tuning Capacitors”, in ESSCIRC 2012 - 38th European Solid State Circuits Conference “A four-path 60 GHz phased-array receiver with injection-locked LO, hybrid beamforming and analog baseband section in 90 nm CMOS”, in 2012 IEEE Radio Frequency Integrated Circuits Symposium “A 52-66GHz Subharmonically Injection-Locked Quadrature Oscillator with 10GHz Locking Range in 40nm LP CMOS”, in 2012 IEEE Radio Frequency Integrated Circuits Symposium “A 9.5mW analog baseband RX section for 60GHz communications in 90nm CMOS”, in 2012 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium “A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range”, in 2012 IEEE International Solid-State Circuits Conference (ISSCC) “A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s”, in 2012 IEEE International Solid-State Circuits Conference (ISSCC) “60 GHz low noise amplifiers with 1 kV CDM protection in 40 nm LP CMOS”, in 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems – SiRF 2011 “A CMOS IQ Direct Digital RF Modulator with Embedded RF FIR-Based Quantization Noise Filter”, in IEEE European Solid-State Circuits Conference (ESSCIRC) 2010 “A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC) “A 40 nm LP CMOS PLL for high-speed mm-wave communication”, in Proceedings of the ESSCIRCཆ conference, Seville, 13-17 Sept. 2010 “CMOS radio integration for high-datarate 60GHz applications”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Riding the mm-waves, destination many Gbits/s”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS”, in International Solid-State Circuits Conference, digest of technical papers 2009 “A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet 2008 “Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS”, in Proceedings of ESSCIRC 2008 “A 7.6 mW 1.75 GS/s 5 bit Flash A/D Converter in 90 nm Digital CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “VCO design for 60 GHz applications using differential shielded inductors in 0.13 �m CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A 400 � W, 4.7-6.4 GHz VCO under an above-IC inductor in 45 nm CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Perspective of RF design in future planar and FinFET CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A 400uW, 4.7-6.4GHz 45nm CMOS VCO with active area underneath its Above-IC Inductor”, in 2008 IEEE 58th Electronic Components and Technology Conference “A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS”, in 2008 IEEE International Solid-State Circuits Conference (ISSCC) “A single-inductor, dual-band VCO in a 0.06mm2, 5.6GHz multistandard front-end in 90nm digital CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A 400uW, 4.7-6.4GHz VCO under an Above-IC inductor in 45nm CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Inductor-Based ESD Protection under CDM-like ESD Stress Conditions for RF Applications”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A 52 GHz Phased-Array Receiver Front-End in 90nm Digital CMOS”, in 2008 IEEE International Solid-State Circuits Conference (ISSCC) “Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet 2007 “Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS”, in 2007 IEEE Asian Solid-State Circuits Conference (A-SSCC) “A Switchable Low-Area 2.4-and-5 GHz Dual-Band LNA in Digital CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A 5 kV HBM transformer-based ESD protected 5-6 GHz LNA”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A Bondpad-Size Narrowband LNA for Digital CMOS”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “A low-power 6.3 GHz FBAR overtone-based oscillator in 90 nm CMOS technology”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Impact of sampling jitter on mostly-digital architectures for UWB bio-medical applications”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet 2006 “Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet 2004 “Identifying the main nonlinear contributions: Use of multisine excitations during circuit design”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Identification of contributions to nonlinear circuit behavior caused by multitone excitation”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “ESD Protection for 5.5 GHz LNA in 90 nm RF CMOS - Implementation Concepts, Constraints and Solutions”, in Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet “Impact of front-end effects on the performance of downlink OFDM-MIMO transmission”, in IEEE Radio and Wireless Conference (RAWCON 2004), Atlanta, GA, September 19-22, 2004 “OFDM-MIMO WLAN AP front-end gain and phase mismatch calibration”, in IEEE Radio and Wireless Conference (RAWCON 2004), Atlanta, GA, September 19-22, 2004 Book Publications 2015 “Data Transmission at Millimeter Waves: Exploiting the 60 GHz Band on Silicon” 2010 “A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS”, in Conference proceedings of European Solid-State Circuits Conference (ESSCIRC) Other Publications 2013 “Basics of 60GHz LNA and PA design in CMOS”, in 2013 IEEE International Solid-State Circuits Conference 2010 “Nonlinear distortion analysis of circuits and systems”, in presentation of tutorial at ISCAS 2010, May 30th-June 2nd 2010 Paris, France 2004 “Performance degradation of RF circuits due to impact of digital switching noise”, in URSI-forum 2004, Broadband Communications, Brussels, December 10, 2004
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