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A 52 GHz Phased-Array Receiver Front-End in 90nm Digital CMOS This publication appears in: IEEE Journal of Solid-State Circuits, December 2008 Authors: K. Scheir, S. Bronckers, J. Borremans, P. Wambacq and Y. Rolain Volume: 43 Pages: 2651-2659 Publication Date: Dec. 2008
Abstract: The commercial potential of the 60 GHz band, in combintation with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz for a low area and power consumption of respectively 0.1 mm2 and 65mW. The presented reciever targets 60 GHz communication where beamforming is required.
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