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A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS This publication appears in: IEEE JOURNAL OF SOLID-STATE CIRCUITS Authors: B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq and G. Van Der Plas Volume: 44 Issue: 3 Pages: 874-882 Publication Date: Mar. 2009
Abstract: A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area. The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption. INL and DNL after calibration are smaller than 0.3 LSB, with an SNDR of 29.9 dB at low frequencies and above 27.5 dB up to the Nyquist frequency. The converter consumes 2.2 mW from a 1 V supply, yielding a FoM of 50 fJ per conversion step and occupies 0.02 mm^2 in a 90 nm 1P9M digital CMOS process.
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