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A 4.1mW 3.5GS/s 6b time interleaved ADC in 40nm CMOS This publication appears in: IEEE Transactions on Microwave Theory and Techniques Authors: S. D'amico, A. Spagnolo, A. Donno, V. Chironi, P. Wambacq and A. Baschirotto Volume: 62 Issue: 8 Pages: 1724-1735 Publication Year: 2014
Abstract: A low-power analog baseband section suitable for 60-GHz receivers using orthogonal frequency-division multiplexing (OFDM) with 16 quadrature amplitude modulation (16-QAM) modulation is presented in this paper. Power efficiency is achieved by combining active-RC with source-follower-based topologies in order to synthesize a custom sixth-order transfer function. The complete chain consists of the cascade of a first-order transimpedance amplifier with finely programmable gain, a fourth-order source-follower-based filter, and a coarse gain first-order programmable gain amplifier. The prototype is implemented in 90-nm CMOS. It achieves a 1-GHz cutoff frequency and programmable gain from 0 to 20 dB with 1-dB step control, drawing 9.5 mA (0Nj dB gain range) or 10.8 mA (10ᆨ dB gain range) from a 1-V supply. An 8.2-dBm third-order input intercept point and a 끙-dBm/Hz input-referred noise power density are measured at 0- and 20-dB gain, respectively. The entire circuit occupies an area of 400 � 390 �m2.
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