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A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS This publication appears in: IEEE Transactions on Circuits and Systems II: Express Briefs Authors: A. Spagnolo, B. Verbruggen, P. Wambacq and S. D'amico Volume: 61 Issue: 7 Pages: 466-470 Publication Year: 2014
Abstract: This brief presents an improved timing scheme for a 4� interleaved 6-bit pipelined binary search (PLBS) analog-to-digital converter (ADC). The individual channel consists of a calibrated fully dynamic PLBS architecture with a 1-bit folding front-end. This work enhances the ADC conversion rate up to 3.5 GS/s, for 4.1-mW power consumption. The peak spurious-free dynamic range and signal-to-noise-plus-distortion ratio (SNDR) are 44.1 and 31.2 dB, respectively, measured for low input frequency. With near-Nyquist input frequency, the SNDR drops to 29.5 dB, yielding an energy-per-conversion step of 48 fJ. The prototype has been fabricated in a 40-nm low-power digital CMOS process. The ADC active area is 250 � 120 �m2.
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