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@InProceedings{Pub_8882, author = {A. Spagnolo, B. Verbruggen, S. D'amico and P. Wambacq}, title={A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS}, booktitle = {European Solid State Circuits Conference (ESSCIRC)}, publisher = {IEEE}, year={2014} }
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