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A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS Host Publication: European Solid State Circuits Conference (ESSCIRC) Authors: A. Spagnolo, B. Verbruggen, S. D'amico and P. Wambacq Publisher: IEEE Publication Year: 2014 ISBN: 978-1-4799-5694-4
Abstract: A 7b time interleaved hybrid ADC in 40nm CMOS is presented. The ADC consists of two pipelined stages and combines an intrinsically linear SAR with a fully calibrated binary search architecture to achieve energy efficiency. The first stage of each channel consists of a 3b SAR followed by a dynamic amplifier merged with a comparator. The second stage is a 3b comparator-based asynchronous binary search with threshold calibration to compensate amplifier nonlinearity. The calibration references are generated on chip by using the DAC embedded in the first stage. The prototype achieves a peak SNDR of 38dB at 3.5GS/s while consuming approximately 6.2mW.
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