Title: Design of 100 Gbaud optical communication circuits using a CMOS-InP co-integrated technology

Promoter: Piet Wambacq

Whether wired or wireless, the global data traffic will not stop. Imagine that, according to latest statistics provided by [Cisco VNI Mobile, 2019], it has been observed that the worldwide fixed internet traffic is increasing by 2-fold every 3 years, and that this trend is still growing. This increasing demand for data becomes in particular clear during the coronavirus pandemic. High datarates are an important need to fill for applications like home-office as well as home-entertainment.

But how does the hardware cope with this trend nowadays? The article [Daly, SSC-Magazine, 2019] for instance reports that the per-pin-data rate is continuing to grow by 2-fold every 4 years and the amount of pins per package by 2-fold every 6 years to catch-up the global need for more data. Moreover, another article [Dehlaghi, SSC-Magazine, 2019] points out that linecards in datacenter switches will need to process more than 25 TB/s system bandwidth in the near future. This means for wired electrical high-speed transmitters that minimum 178 Gbps per pin datarate must be reached.

Is 178 Gbps per pin data rate feasible with CMOS-technology nowadays? Comparing the transit frequency fT and maximum oscillation frequency fmax across common commercial technologies like FinFET, planar CMOS or FDSOI, one can clearly see that designers will approach more and more the upper boundary. Furthermore, even large corporations seem to face difficulties to reach for more datarates without sacrificing ESD-protection. In [Kim, JSSC, 2019] they use a more sophisticated bandwidth extension circuits to increase further datarates up to 112 Gbps with a high level of ESD protection, while in [Toprak-Deniz, JSSC, 2020] they managed to reach highest datarates of 128 Gbps and best power efficiency in CMOS-technology, but with a weaker ESD protection compared to their competitors.

Those observations give the following options and potential research perspectives in how to increase the datarate of wireline transmitters:
• By innovating ESD-protection
• By innovating bandwidth-extension circuits
• By including III/V semiconductors
This research includes III/V semiconductors to seek for more speed. Comparing III/V semiconductor devices like InP-HBT (Indium Phosphide-Heterojunction Bipolar Transistors) with commercial CMOS technologies, InP-HBTs contain more fT and much more fmax, however they entail other drawbacks. On the one hand their yield in the processing is worse compared to CMOS, thus designing complex circuits will be difficult and digital circuits with InP are out of the question. On the other hand, using just InP-HBTs is a power hungry approach, as the latest publication [Nagatani, BCICTS, 2019] about the fastest InP-TX reported so far is showing (2 Watt!).

To overcome those trade-offs, this PhD research is examining a novel approach: designing high speed and power efficient wireline transmitters by combining CMOS- and InP-technology. The idea behind this strategy is to combine the advantages of both technologies in one integrated transmitter:
1. Using CMOS-technology to enable high integration level and low power.
2. Using InP for maximum bandwidth/speed as well as larger swing.

When reaching target symbolrates beyond 100 Gbaud and a power efficiencies below 1mW/Gbps (1pJ/b) to compete with the state-of-the-art, with the gained knowledge and experience one can develop such wireline electrical transmitters which will be required in all electrical and optical applications where high speed serial data is transmitted and processed. To be more specific: everywhere where mobile devices, social networks, video streaming and multimedia services are offered. Companies such as Google, Facebook, Amazon, Youtube and Netflix, but also VSC (Vlaams Supercomputer Center) located in the Flemish Region of Belgium process huge amounts of data in cloud data centers, in particular in tough times during the coronavirus pandemic. Furthermore, the anticipated rollout of 5G and artificial intelligence (AI) is set to put further pressure on all data centers.

To conclude, this doctoral project will give a unique opportunity to research the variety of wireline high speed serial- and parallel-link transmitter architectures, to model and design with compound semiconductors like InP as well as to explore innovative and novel architectures by combining CMOS- and InP-technology targeting for electrical and optical applications.

More information can be found here.