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Click here for this list in IEEE format.
Journal Publications 2020 “Characterization and Modeling of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs”, in IEEE Transactions on Electron Devices “Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs”, in IEEE Transactions on Electron Devices “(Invited) Advanced Transistors for High Frequency Applications”, in ECS Transactions “Low-Frequency Noise Investigation of GaN/AlGaN Metal–Oxide–Semiconductor High-Electron-Mobility Field-Effect Transistor With Different Gate Length and Orientation”, in IEEE Transactions on Electron Devices “Total-Ionizing-Dose Effects in InGaAs MOSFETs With High-k Gate Dielectrics and InP Substrates”, in IEEE Transactions on Nuclear Science “Comparison of temperature dependent carrier transport in FinFET and gate-all-around nanowire FET”, in Applied Sciences (Switzerland) “Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs”, in IEEE Journal of the Electron Devices Society 2019 “Ge Devices: A Potential Candidate for Sub-5-nm Nodes?”, in IEEE Transactions on Electron Devices “Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs”, in IEEE Transactions on Electron Devices “Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs”, in IEEE Transactions on Electron Devices “Understanding the impact of time-dependent random variability on analog ICs: From single transistor measurements to circuit simulations”, in IEEE Transactions on very large scale integration (VLSI) Systems “Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations”, in IEEE Transactions on very large scale integration (VLSI) Systems 2018 “A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability”, in Microelectronics Reliability “Built-in sheet charge as an alternative to dopant pockets in tunnel field-effect transistors”, in IEEE Journal of the Electron Devices Society “3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability”, in IEEE Transactions on Electron Devices “Junctionless versus inversion-mode lateral semiconductor nanowire transistors”, in Journal of Physics: Condensed Matter Conference Publications 2020 “Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications”, in 2020 IEEE International Reliability Physics Symposium, IRPS 2020 “Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures”, in 2020 IEEE International Reliability Physics Symposium, IRPS 2020 2019 “Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications”, in 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019 “Device-, Circuit-Block-level evaluation of CFET in a 4 track library”, in 39th Symposium on VLSI Technology, VLSI Technology 2019 “Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications”, in 39th Symposium on VLSI Technology, VLSI Technology 2019 “Key challenges and opportunities for 3D sequential integration”, in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 “First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers”, in 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 “CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and Performance”, in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 “First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering”, in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 “Physical Insights on Steep Slope FEFETs including Nucleation-Propagation and Charge Trapping”, in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 “Trap-aware compact modeling and power-performance assessment of III-V tunnel FET”, in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 2018 “Semiconductor Technologies for next Generation Mobile Communications”, in 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 “Scaling CMOS beyond Si FinFET: An analog/RF perspective”, in 48th European Solid-State Device Research Conference, ESSDERC 2018 “An in-depth study of high-performing strained germanium nanowires pFETs”, in 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 “Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells”, in 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 “3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability”, in 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 “Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology”, in 63rd IEEE International Electron Devices Meeting, IEDM 2017 “The impact of sequential-3D integration on semiconductor scaling roadmap”, in 63rd IEEE International Electron Devices Meeting, IEDM 2017 “3D technologies for analog/RF applications”, in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 “Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling”, in 2018 International Conference on IC Design and Technology, ICICDT 2018 “Cost Effective FinFET Platform for Stand Alone DRAM 1Y and beyond Memory Periphery”, in 10th IEEE International Memory Workshop, IMW 2018 “A 23 GHz Low-Phase-Noise Transformer-Feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz”, in A 23 GHz Low-Phase-Noise Transformer-Feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz “Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET”, in Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET 2017 “A fully-integrated method for RTN parameter extraction”, in Symposium on VLSI Technology “Defect-based compact modeling for RTN and BTI variability”, in International reliability symposium “Back-gate bias effect on UTBB-FDSOI non-linearity performance”, in European Solid-State Device Research Conference “Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements”, in oint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 “Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs”, in oint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 “Characterization and modeling of n-channel bulk FinFETs from DC to high frequency”, in 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 2016 “A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS”, in 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 “60-GHz CMOS TX/RX chipset on organic packages with integrated phased-array antennas”, in 10th European Conference on Antennas and Propagation, EuCAP 2016 Book Publications 2020 “Defect-based compact modeling of random telegraph noise”, in Noise in Nanoscale Semiconductor Devices
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