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Journal Publications 2020 B. Parvais, R. Yasser Gomaa Mohamed Elkashlan, P. Wambacq, U. Peralagu, A. Vais, A. Alian, L. Witters, Y. Mols, A. Walke, M. Ingels, H. Yu, V. Putcha, A. Khaled, R. Rodriguez, A. Sibaja-Hernandez, S. Yadav, M. Baryshnikova, G. Mannaert, R. Alcotte, B. Kunert, E. Simoen, E. Zhao, B. De Jaeger, D. Fleetwood, R. Langer, M. Zhao, N. Waldron and N. Collaert, “(Invited) Advanced Transistors for High Frequency Applications,” ECS Transactions, vol. 97, no. 27, pp. 27-38, May. 2020. A. Beckers, F. Jazaeri, A. Grill, S. Narasimhamoorthy, B. Parvais and C. Enz, “Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs,” IEEE Journal of the Electron Devices Society, vol. 8, pp. 780-788, 2020. C. Gupta, A. Gupta, S. Tuli, E. Bury, B. Parvais and A. Dixit, “Characterization and Modeling of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs,” IEEE Transactions on Electron Devices, vol. 67, no. 1, pp. 4-10, Jan. 2020. K. Takakura, V. Putcha, E. Simoen, A. R. Alian, U. Peralagu, N. Waldron, B. Parvais and N. Collaert, “Low-Frequency Noise Investigation of GaN/AlGaN Metal–Oxide–Semiconductor High-Electron-Mobility Field-Effect Transistor With Different Gate Length and Orientation,” IEEE Transactions on Electron Devices, vol. 67, no. 8, pp. 3062-3068, Aug. 2020. R. Yasser Gomaa Mohamed Elkashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais and N. Collaert, “Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs,” IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4592-4596, Sep. 2020. S. Bonaldo, E. Xia Zhang, S. E. Zhao, V. Putcha, B. Parvais, D. Linten, S. Gerardin, A. Paccagnella, R. A. Reed, R. D. Schrimpf and D. M. Fleetwood, “Total-Ionizing-Dose Effects in InGaAs MOSFETs With High-k Gate Dielectrics and InP Substrates,” IEEE Transactions on Nuclear Science, vol. 67, no. 7, pp. 1312-1319, Jul. 2020. S. Kim, J. Kim, D. Jang, R. Ritzenthaler, B. Parvais, J. Mitard, H. Mertens, T. Chiarella, N. Horiguchi and J. Woo Lee, “Comparison of temperature dependent carrier transport in FinFET and gate-all-around nanowire FET,” Applied Sciences (Switzerland), vol. 10, no. 8, Apr. 2020. 2019 M. Simicic, P. Weckx, B. Parvais, P. Roussel, B. Kaczer and G. Gielen, “Understanding the impact of time-dependent random variability on analog ICs: From single transistor measurements to circuit simulations,” IEEE Transactions on very large scale integration (VLSI) Systems, vol. 27, no. 3, pp. 601-610, Mar. 2019. N. Sharan, G. Eneman, N. Collaert, B. Parvais, A. Spessot, A. Mocuta, K. A. Shaik, D. Jang, P. Schuddinck, D. Yakimets, m. garcia bardon, J. Mitard, H. Arimura and F. M. Bufler, “Ge Devices: A Potential Candidate for Sub-5-nm Nodes?,” IEEE Transactions on Electron Devices, vol. 66, no. 11, pp. 4997-5002, Nov. 2019. R. Singh, K. Aditya, A. Veloso, B. Parvais and A. Dixit, “Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs,” IEEE Transactions on Electron Devices, vol. 66, no. 8, pp. 3279-3285, Aug. 2019. Y. Xiang, A. S. Verhulst, D. Yakimets, B. Parvais, A. Mocuta and G. Groeseneken, “Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs,” IEEE Transactions on Electron Devices, vol. 66, no. 6, pp. 2802-2808, Jun. 2019. 2018 B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, J. Franco, A. Walke, V. Deshpande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, E. Vecchio, T. Zheng, W. Vanherle, A. Hikavyy, B. T. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, N. Waldron, V. De Heyn, D. Mocuta and N. Collaert, “3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability,” IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 5165-5171, Nov. 2018. A. Veloso, P. Matagne, E. Simoen, B. Kaczer, G. Eneman, H. Mertens, D. Yakimets, B. Parvais and D. Mocuta, “Junctionless versus inversion-mode lateral semiconductor nanowire transistors,” Journal of Physics: Condensed Matter, vol. 30, no. 38, Sep. 2018. B. Kaczer, J. Franco, P. Weckx, P. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais, F. Catthoor, G. Rzepa, M. Waltl and T. Grasser, “A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability,” Microelectronics Reliability, vol. 81, pp. 186-194, Feb. 2018. D. Verreck, A. S. Verhulst, Y. Xiang, D. Yakimets, S. El Kazzi, B. Parvais, G. Groeseneken, N. Collaert and A. Mocuta, “Built-in sheet charge as an alternative to dopant pockets in tunnel field-effect transistors,” IEEE Journal of the Electron Devices Society, vol. 6, pp. 658-663, May. 2018. Conference Publications 2020 A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl and I. Radu, “Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures,” in 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Institute of Electrical and Electronics Engineers Inc, Apr. 2020, pp. 6. V. Putcha, E. Bury, J. Franco, A. Walke, U. Peralagu, A. Alian, B. Kaczer, N. Waldron, D. Linten, B. Parvais and N. Collaert, “Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications,” in 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Institute of Electrical and Electronics Engineers Inc, Apr. 2020. 2019 B. Parvais, E. Rosseel, L. Peng, L. Teugels, A. Vandooren, J. Franco, A. Mallik, A. Hikkavyy, N. Rassoul, G. Jamieson, F. Inoue, G. Verbinnen, E. Vecchio, T. Zheng, N. Waldron, J. Boemmels, V. De Heyn, D. Mocuta and N. Collaert, “Key challenges and opportunities for 3D sequential integration,” in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc, Feb. 2019. B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, A. Khaled, J. Franco, A. Walke, N. Rassoul, P. Matagne, H. Debruyn, G. Jamieson, F. Inoue, E. Vecchio, T. Zheng, D. Radisic, W. Vanherle, A. Hikavyy, B. T. Chan, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, N. Waldron, V. De Heyn, J. Boemmels, N. Collaert and D. Mocuta, “Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications,” in 39th Symposium on VLSI Technology, VLSI Technology 2019, Institute of Electrical and Electronics Engineers Inc, Jun. 2019. B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, J. Franco, A. Walke, V. Deshpande, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, E. Vecchio, T. Zheng, W. Vanherle, A. Hikavyy, G. Mannaert, B. T. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, J. Boemmels, D. Mocuta and N. Collaert, “First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers,” in 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, Institute of Electrical and Electronics Engineers Inc, Jan. 2019. D. Yan, M. Ingels, G. Mangraviti, Y. Liu, B. Parvais, N. Waldron, N. Collaert and P. Wambacq, “Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications,” in 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, Institute of Electrical and Electronics Engineers Inc, Jun. 2019. A. Vais, R. Alcotte, M. Ingels, P. Wambacq, B. Parvais, R. Langer, B. Kunert, N. Waldron, N. Collaert, Y. Mols, A. S. Hernandez, A. Walke, M. Baryshnikova, G. Mannaert and V. Deshpande, “First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering,” in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, Institute of Electrical and Electronics Engineers Inc, Dec. 2019. P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, B. Parvais, D. Verkest and A. Mocuta, “Device-, Circuit-Block-level evaluation of CFET in a 4 track library,” in 39th Symposium on VLSI Technology, VLSI Technology 2019, Institute of Electrical and Electronics Engineers Inc, Jun. 2019. U. Peralagu, B. De Jaeger, D. M. Fleetwood, P. Wambacq, B. Parvais, N. Waldron, N. Collaert, A. Alian, V. Putcha, A. Khaled, R. Rodriguez, A. Sibaja-Hernandez, S. Chang and E. Simoen, “CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and Performance,” in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, Institute of Electrical and Electronics Engineers Inc, Dec. 2019. Y. Xiang, A. Verhulst, B. Parvais, N. Horiguchi, G. Groeseneken, M. Garcia Bardon, M. Nur K. Alam, M. Thesberg, B. Kaczer, P. Roussel, M. I. Popovici and L. A. Ragnarsson, “Physical Insights on Steep Slope FEFETs including Nucleation-Propagation and Charge Trapping,” in 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, Institute of Electrical and Electronics Engineers Inc, Dec. 2019. Y. Xiang, D. Yakimets, s. sant, E. Memisevic, m. garcia bardon, A. S. Verhulst, B. Parvais, A. Schenk, L. Erik Wernersson and G. Groeseneken, “Trap-aware compact modeling and power-performance assessment of III-V tunnel FET,” in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc, Feb. 2019, pp. 3. 2018 B. Parvais, E. Rosseel, L. Peng, L. Teugels, A. Vandooren, J. Franco, A. Mallik, A. Walke, V. Deshpande, A. Hikavyy, N. Rassoul, G. Jamieson, F. Inoue, G. Verbinnen, E. Vecchio, T. Zheng, N. Waldron, V. De Heyn, D. Mocuta and N. Collaert, “Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling,” in 2018 International Conference on IC Design and Technology, ICICDT 2018, Institute of Electrical and Electronics Engineers Inc, Jun. 2018, pp. 4. B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. Van Liempc, A. Veloso, A. Vandooren, N. Waldron, P. Wambacq, N. Collaert and D. Verkest, “Scaling CMOS beyond Si FinFET: An analog/RF perspective,” in 48th European Solid-State Device Research Conference, ESSDERC 2018, Editions Frontieres, Neuily sur Seine, France, Oct. 2018, pp. 4. B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, J. Franco, A. Walke, V. Desphande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, E. Vecchio, T. Zheng, W. Vanherle, A. Hikavyy, B. T. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, N. Waldron, V. De Heyn, D. Mocuta and N. Collaert, “3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability,” in 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Institute of Electrical and Electronics Engineers Inc, Oct. 2018, pp. 2. B. Parvais, P. Van Marcke, H. Mertens, J. Mitard, D. Jang, G. Eneman, H. Arimura, O. Richard, E. Capogreco, H. Bender, R. Ritzenthaler, A. Hikavyy, R. Loo, H. Dekkers, F. Sebaai, A. Milenin, N. Horiguchi, A. Mocuta, D. Mocuta and N. Collaert, “An in-depth study of high-performing strained germanium nanowires pFETs,” in 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Institute of Electrical and Electronics Engineers Inc, Oct. 2018, pp. 2. B. Parvais, Y. Xiang, D. Yakimets, s. sant, E. Memisevic, m. garcia bardon, a. verhulst, A. Schenk, L. Wernersson and G. Groeseneken, “Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET,” in Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET, 2018. B. Parvais, Z. Zong, C. Tsai, F. Pepe, P. Wambacq, G. Mangraviti, Y. Liu and Q. Shi, “A 23 GHz Low-Phase-Noise Transformer-Feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz,” in A 23 GHz Low-Phase-Noise Transformer-Feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz, 2018. A. Mallik, A. Vandooren, L. Witters, A. Walke, J. Franco, Y. Sherazi, P. Weckx, D. Yakimets, M. Bardon, B. Parvais, P. Debacker, B. W. Ku, A. Mocuta, D. Mocuta, N. Collaert and P. Raghavan, “The impact of sequential-3D integration on semiconductor scaling roadmap,” in 63rd IEEE International Electron Devices Meeting, IEDM 2017, Institute of Electrical and Electronics Engineers Inc, Jan. 2018. A. Spessot, N. Sharan, H. Oh, R. Ritzenthaler, E. Dentoni Litta, B. O'Sullivan, A. Mallik, A. De Keersgieter, B. Parvais, Y. Sherazi, V. Machkaoutsan, C. Kim, P. Fazan, D. Mocuta, A. Mocuta and N. Horiguchi, “Cost Effective FinFET Platform for Stand Alone DRAM 1Y and beyond Memory Periphery,” in 10th IEEE International Memory Workshop, IMW 2018, Institute of Electrical and Electronics Engineers Inc, Jun. 2018, pp. 4. A. Vandooren, B. Parvais, A. Walke, A. Vais, C. Merckling, D. Lin, N. Waldron, P. Wambacq, D. Mocuta and N. Collaert, “3D technologies for analog/RF applications,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers Inc, Mar. 2018, pp. 3. D. Yakimets, M. Garcia Bardon, D. Jang, P. Schuddinck, Y. Sherazi, P. Weckx, K. Miyaguchi, B. Parvais, P. Raghavan, A. Spessot, D. Verkest and A. Mocuta, “Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology,” in 63rd IEEE International Electron Devices Meeting, IEDM 2017, Institute of Electrical and Electronics Engineers Inc, Jan. 2018. M. Garcia Bardon, Y. Sherazi, D. Jang, D. Yakimets, P. Schuddinck, R. Baert, H. Mertens, L. Mattii, B. Parvais, A. Mocuta and D. Verkest, “Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells,” in 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Institute of Electrical and Electronics Engineers Inc, Oct. 2018, pp. 2. N. Collaert, A. Alian, V. Deshpande, M. Ingels, V. Putcha, A. Sibaja-Hernandez, B. Van Liempd, A. Vais, A. Vandooren, A. Walke, D. Linten, B. Parvais, P. Wambacq and N. Waldron, “Semiconductor Technologies for next Generation Mobile Communications,” in 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018, Institute of Electrical and Electronics Engineers Inc, Dec. 2018. 2017 B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond and D. Flandre, “Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements,” in oint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017, Institute of Electrical and Electronics Engineers Inc, Jun. 2017, pp. 3. B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre and J. P. Raskin, “Back-gate bias effect on UTBB-FDSOI non-linearity performance,” in European Solid-State Device Research Conference, Editions Frontieres, Neuily sur Seine, France, Oct. 2017, pp. 4. M. Simicic, S. Morrison, B. Parvais, P. Weckx, B. Kaczer, K. Sawada, H. Ammo, S. Yamakawa, K. Nomoto, M. Ohno, D. Linten, D. Verkest, P. Wambacq, G. Groeseneken and G. Gielen, “A fully-integrated method for RTN parameter extraction,” in Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc, Jul. 2017. P. Weckx, M. Simicic, K. Nomoto, M. Ono, B. Parvais, B. Kaczer, P. Raghavan, D. Linten, K. Sawada, H. Ammo, S. Yamakawa, A. Spessot, D. Verkest and A. Mocuta, “Defect-based compact modeling for RTN and BTI variability,” in International reliability symposium, Institute of Electrical and Electronics Engineers Inc, May. 2017. R. Singh, P. Kushwaha, S. Ghosh, B. Parvais, Y. S. Chauhan and A. Dixit, “Characterization and modeling of n-channel bulk FinFETs from DC to high frequency,” in 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017, Institute of Electrical and Electronics Engineers Inc, Dec. 2017, pp. 2. V. Kilchytska, B. Kazemi Esfeh, C. Gimeno, B. Parvais, N. Planes, M. Haond and D. Flandre, “Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs,” in oint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017, Institute of Electrical and Electronics Engineers Inc, Jun. 2017, pp. 4. 2016 B. Parvais, P. Wambacq, A. Mercha, D. Verkest, A. Thean, K. Sawada, K. Nomoto, T. Oishi and H. Ammo, “A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS,” in 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Institute of Electrical and Electronics Engineers Inc, Jan. 2016. S. Brebels, K. Khalaf, G. Mangraviti, K. Vaesen, M. Libois, B. Parvais, V. Vidojkovic, V. Szortyka, A. Bourdoux, P. Wambacq, C. Soens and W. Van Thillo, “60-GHz CMOS TX/RX chipset on organic packages with integrated phased-array antennas,” in 10th European Conference on Antennas and Propagation, EuCAP 2016, Institute of Electrical and Electronics Engineers Inc, May. 2016, pp. 6. Book Publications 2020 P. Weckx, B. Kaczer, M. Simicic, B. Parvais and D. Linten, “Defect-based compact modeling of random telegraph noise,” in Noise in Nanoscale Semiconductor Devices, Springer International Publishing AG, Apr. 2020, pp. 16.
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