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Junctionless versus inversion-mode lateral semiconductor nanowire transistors This publication appears in: Journal of Physics: Condensed Matter Authors: A. Veloso, P. Matagne, E. Simoen, B. Kaczer, G. Eneman, H. Mertens, D. Yakimets, B. Parvais and D. Mocuta Volume: 30 Issue: 38 Publication Date: Sep. 2018
Abstract: This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technological challenges, looking in particular at doping strategies. A comprehensive review of junctionless versus inversion-mode type of transistors is here presented, evaluating the impact on the devices' operation mode and on device properties such as: variability, reliability, noise, DC and analog/RF performance. We also discuss the potential for further manufacturable co-integration options.
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