|
|
3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability This publication appears in: IEEE Transactions on Electron Devices Authors: B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, J. Franco, A. Walke, V. Deshpande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, E. Vecchio, T. Zheng, W. Vanherle, A. Hikavyy, B. T. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, N. Waldron, V. De Heyn, D. Mocuta and N. Collaert Volume: 65 Issue: 11 Pages: 5165-5171 Publication Date: Nov. 2018
Abstract: 3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V
G= V
th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metalǃ interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.
|
|
