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The impact of sequential-3D integration on semiconductor scaling roadmap Host Publication: 63rd IEEE International Electron Devices Meeting, IEDM 2017 Authors: A. Mallik, A. Vandooren, L. Witters, A. Walke, J. Franco, Y. Sherazi, P. Weckx, D. Yakimets, M. Bardon, B. Parvais, P. Debacker, B. W. Ku, A. Mocuta, D. Mocuta, N. Collaert and P. Raghavan Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Jan. 2018 ISBN: 9781538635599
Abstract: The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. SequentialDžD (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.
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