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A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks Host Publication: International Symposium on Applied Reconfigurable Computing Authors: B. da Silva Gomes, L. Segers, A. Braeken, K. Steenhaut and A. Touhafi Publication Date: May. 2018 Number of Pages: 13
Abstract: Microphone arrays add an extra dimension to sensory information from Wireless Sensor Networks by determining the direction of the sound instead of only its intensity. Microphone arrays, however, need to be flexible enough to adapt their characteristics to realistic acoustic environments, while being power efficient, as they are battery-powered. Consequently, there is a clear need to design adaptable microphone array nodes enabling quality aware distributed sensing and prioritizing low power consumption. In this paper a novel dynamic, scalable and energy-efficient FPGA-based architecture is presented. The proposed architecture applies the Delay-and-Sum beamforming technique to the single-bit digital audio from the MEMS microphones to obtain the relative sound power in the time domain. As a result, the resource consumption is drastically reduced, making the proposed architecture suitable for low-power Flash-based FPGAs. In fact, the architecture’s power consumption estimation can become as low as 649 �W per microphone.
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