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A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter Host Publication: 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Authors: K. Raczkowski, N. Markulic, B. Hershberg, J. Van Driessche and J. Craninckx Publisher: IEEE Publication Year: 2014 Number of Pages: 4 ISBN: 978-1-4799-3862-9
Abstract: This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves ᆺ dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional spur of ᆿ dBc is present. In-band phase noise is at the level of 뀰 dBc/Hz. The class-B VCO used can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9V and 1.8V supplies.
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