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A Fractional-n subsampling PLL based on a digital-to-time converter Host Publication: Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2016 39th International Convention on Authors: N. Markulic, K. Raczkowski, P. Wambacq and J. Craninckx Publication Date: Jul. 2016
Abstract: The paper presents a subsampling PLL which uses a 10-bit, 0.5 ps unit step Digital-to-Time Converter (DTC) in the phase-error comparison path for the fractional-N lock. The gain and nonlinearity of the DTC can be digitally calibrated in the background while the PLL operates normally. During fractional multiplication of a 40 MHz reference to frequencies around 10 GHz, the measured jitter is in the range from 176 to 198 fs. The worst measured fractional spur is ᇍ dBc and the in-band phase noise performance of the PLL is 뀴 dBc/Hz. The presented analog PLL in advanced 28 nm CMOS achieves a figure-of-merit (FOM) of 낾.6 dB that compares well to the recent state-of-the-art.
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