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A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS Host Publication: 2014 Symposium on VLSI Circuits Authors: B. Verbruggen, K. Deguchi, B. Malki and J. Craninckx Publisher: IEEE Publication Date: Jun. 2014 ISBN: 978-1-4799-3327-3
Abstract: We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply. External Link.
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