|
A Low-cost and Low-power IEEE 802.15.4-compliant System-On-Chip for Tracking Application in Medical Environment Host Publication: Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet Authors: T. Bey, A. Touhafi and G. Cornetta Publication Year: 2010
Abstract: We present the design of a baseband System-On-Chip for tracking applications in the medical environment based on the IEEE 802.15.4 standard which can be used to track patient location in hospitals.
An issue in the commonly named healthcare pervasive computing is keeping track of patients location in the medical environment. Several applications can benefit, for instance, to monitor patients affected by mental illness moving out from the hospital designated areas or to perform location-based medical services where different analyses are carried out in relation to patient's place.
To design an optimal solution requires taking into consideration some topics. We are considering wearable devices which patients have on, at mininum space and weight where battery life must be improved and power consumption reduced.
IEEE 802.15.4 protocolis extensively used in medical sensing and health care to send vital signs and location information due to its low-power consumption orientation and transmission rate. It describes the Physical (PHY) and Medium Access Control (MAC) layers for Low-rate Wireless Personal Area Networks (LR-W-PAN).
The presented System-on-Chip uses an ARM7TDMI processor due to its recognized low-power consumption clocked at 8 MHz and works on an bus based on the AMBA AHB-Lite architecture. It utilizes 16 kb of Flash-ROM to store the MAC primitives implementation and 8 kb of SRAM. The IEEE 802.15.4 modem is connected through an APB to AHB bridge sharing bus adress space with the interrupt controller and two programmable interval timers. The first one is used to control the system time and helps during network scanning and frame sequence numbers and timestamp generation. The second one is used to put the modem in sleep mode for a period of time to save energy while is not transmitting nor receiving.
The physical layer realization is parted in a digital section as synthetizable VHDL and a RF front end. The RF front was designed and simulated using an Agilent SystemVue model.
The realization of the MAC layer (Figure 3) is divided in a hardware part designed as a VHDL model that consists in: an AES 128-bit implementation, two configurable internal timers, the FCS computation unit, transmission and reception FIFOs, and the PHY digital clock manager and a software realization
which implements the MAC layer primitives.
The actual SoC model was verified using Mentor Graphics Questa Codelink using with an ARM CVE simulation model. FPGA synthesis was performed using Mentor Precision Synthesis on a Virtex 5 xc5vlx50t board.
Future work includes synthesis and co-verification on the FPGA board using an Actel's CoreMP7 ARM7TDMI-S based soft-core.
|
