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CMOS image sensor architecture for high-speed sparse image content readout Host Publication: Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet Authors: A. Dupret, B. Dupont, M. Vasiliu, B. Dierickx and A. Defernez Publisher: Unknown Publisher Publication Date: Jun. 2009
Abstract: Many high-end imaging systems make use of high-speed image sensors. With resolution ranging from 1 to 4 Mpixels and with readout speed of several thousands of frames per second, these image sensors are very large circuits. They consume usually several Watts and are complex to use and interface due to the large amount of high bandwidth parallel analog busses. However, in various cases where high-speed image sensors are required, it appears that the scene contains sparse, yet fugitive, information.
To address this issue, we propose first a novel architecture, for image sensor readout using a pipelined global shutter image sensor in which the readout is asynchronous and not scanned sequentially. Content aware pixels use a dominolike asynchronous readout and do not suffer from ambiguity during the decoding of the addresses. The analog data are then retrieved from the single pixels using the asynchronously read addresses. We present the concept and design. We discuss the required payload in term of pixel surface to perform such operation. External Link.
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