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Analog and RF circuits in 45 nm CMOS: planar bulk versus FinFET Host Publication: Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet Authors: P. Wambacq, B. Verbruggen, K. Scheir, J. Borremans, V. De Heyn, G. Van Der Plas, A. Mercha, B. Parvais, V. Subramanian, M. Jurzak, S. Decoutere and S. Donnay Publication Date: Sep. 2006 Number of Pages: 4
Abstract: Scaling to 45 nm node and below might necessitate the use of new processing steps (e.g. new gate stacks) or new device concepts such as FinFETs. Although intrinsic transistor speed increases with scaling, some analog performance parameters tend to degrade. In this paper we show with experimental results and simulations on analog and RF circuits that for high-speed and RF applications, downscaling to 45 nm channel length of bulk devices still improves RF circuit performance, while for low-frequency, high-gain applications FinFET technology offers better circuit performance than planar bulk CMOS.
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