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A 52 GHz Phased-Array Receiver Front-End in 90nm Digital CMOS Host Publication: 2008 IEEE International Solid-State Circuits Conference (ISSCC) Authors: K. Scheir, S. Bronckers, J. Borremans, P. Wambacq and Y. Rolain Publisher: IEEE Publication Date: Feb. 2008 Number of Pages: 1 ISBN: 978-1-4244-2010-0
Abstract: A 52GHz phased-array homodyne receiver front-end with 2 antenna paths is implemented in 90nm digital CMOS. The QVCO and phase selectors provide control over the phase of the LO-signals, allowing beamforming and steering. The receiver achieves a conversion gain of 30dB/path and an NF of 7.1dB/path, yielding a system NF of 4.1dB. The chip consumes 65mW and occupies 0.1mm2.
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