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A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS Host Publication: Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet Authors: K. Scheir, G. Vandersteen, Y. Rolain and P. Wambacq Publication Date: Feb. 2009
Abstract: A 57-toᇖGHz quadrature PLL in low-power 45nm digital CMOS achieves a large tuning range with 2 QVCOs and a tunable injection-locked prescaler. The circuit has quadrature outputs, consumes 78mW from a 1.1V supply, achieves a phase noise of ᇦdBc/Hz at 3MHz offset around 61.6GHz, and has a reference spur level of ᆾdBc.
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