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60 GHz low noise amplifiers with 1 kV CDM protection in 40 nm LP CMOS Host Publication: 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems – SiRF Authors: K. Raczkowski, S. Thijs, J. Tseng, T. Chang, M. Song, D. Linten, B. Nauwelaers and P. Wambacq Publisher: IEEE Publication Year: 2012 ISBN: 978-1-4577-1317-0
Abstract: This paper describes a set of miniature, three-stage 60 GHz LNAs designed in 40 nm LP CMOS. The designs prove effectiveness and ease of use of inductor-based ESD protection schemes applied to mm-wave circuits. The measured ESD protection levels reach 4.5 kV HBM, up to 7.6 A for VFTLP tests and a record of 1 kV CDM. At the same time, the NF of the LNAs is below 8 dB and the gain above 15 dB at 60 GHz, all at 1.1 V supply. These circuits can effectively be used as input stages of a phased array receiver.
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