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Design Technology co-optimization for N10 Host Publication: IEEE 2014 Custom Integrated Circuits Conference Authors: P. Wambacq, D. Verkest, J. Ryckaert, P. Raghavan, R. Baert, M. Garcia Bardon, M. Dusa, A. Mallik, S. Sakhare, B. Vandewalle, B. Chava, K. Croes, M. Dehan, D. Jang, P. Leray, T. Liu, K. Miyaguchi, B. Parvais, P. Schuddinck, P. Weemaes, A. Mercha, J. Bömmels, N. Horiguchi, G. McIntyre, A. Thean, Z. Tokei, S. Cheng and A. Steegen Publisher: IEEE Publication Year: 2014
Abstract: Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.
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