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A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS Host Publication: 40th European Solid-State Circuit Conference Authors: N. Markulic, K. Raczkowski, P. Wambacq and J. Craninckx Publisher: IEEE Publication Date: Sep. 2014 Number of Pages: 4 ISBN: 978-1-4799-5694-4
Abstract: This paper presents a 10-bit, 550-fs step Digitalto-TimeConverter (DTC) used in the phase comparison pathof a fractional-N, TDC-less and divider-less PLL. The DTC isdevised as a single-ended architecture which uses a tunable RCnetwork for delay control. The circuit is optimized for low phasenoise not to limit the in-band phase noise performance of thefabricated PLL. Measured INL and DNL are below 1.8 LSB and0.8 LSB, respectively. The DTC phase noise floor is below 끢dBc/Hz at 0.5 mW power consumption from a 0.9 V supply. At10 GHz output, the in-band phase noise of the PLL with theDTC embedded is 뀱 dBc/Hz. The PLL achieves 270 fs RMSjitter, consuming 26 mW.
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