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Modeling FinFET metal gate stack resistance for 14nm node and beyond Host Publication: 2015 International Conference on IC Design & Technology (ICICDT) Authors: K. Miyaguchi, B. Parvais, L. Ragnarsson, P. Wambacq, P. Raghavan, A. Mercha, A. Mocuta, D. Verkest and A. Thean Publisher: IEEE Publication Year: 2015
Abstract: A FinFET high-k replacement metal gate stack resistance model is proposed. Introduction of non-negligible contact resistance existing in boundaries between metal layers achieves a good model accuracy which is validated by FEM-based simulation results in 14nm and 10nm technology nodes. Impact of the contact resistance on digital and analog circuit is investigated, resulting in 20% degradation of analog speed by 5 O��m2 contact resistance. The derived gate resistance model is applicable to further downscaled FinFET technology.
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