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Lateral versus vertical gate-all-around FETs for beyond 7nm technologies Host Publication: 72nd Device Research Conference (DRC 2014) Authors: D. Yakimets, T. Huynh Bao, M. Garcia Bardon, M. Dehan, N. Collaert, A. Mercha, Z. Tokei, A. Thean, D. Verkest and K. De Meyer Publisher: IEEE Publication Date: Jun. 2014 Number of Pages: 2 ISBN: 978-1-4799-5405-6
Abstract: Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.
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