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Efficient link architecture for on-chip serial links and networks Host Publication: Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet Authors: J. Balachandran, M. Kuijk, G. Carchon, B. Nauwelaers and E. Beyne Publisher: IEEE Publication Date: Nov. 2006 Number of Pages: 4 ISBN: 978-1-4244-0621-0
Abstract: Serial links are an effective solution to address the growing on-chip communication bottlenecks in nano-CMOS technologies. This paper proposes efficient link architecture for on-chip serial links and networks. The proposed solution consists of a pre-emphasized differential driver and receiver interconnected by LC transmission lines. The LC transmission lines are implemented in packaging layers post processed directly above a standard CMOS wafer. The link enables simple register-to-register style data transfer, well suited for on-chip IO. The proposed scheme can offer data rates as high as 12.5 Gbps per channel for less than 0.5pJ of energy per bit on the 0.13 micron technology
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