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A 7.6 mW 1.75 GS/s 5 bit Flash A/D Converter in 90 nm Digital CMOS Host Publication: Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet Authors: B. Verbruggen, P. Wambacq, M. Kuijk and G. Van Der Plas Publisher: IEEE Solid-State Circuits Soc Japan Soc Appl Phys Publication Date: Jun. 2008 Number of Pages: 2 ISBN: 978-1-4244-1804-6
Abstract: A 5 bit 1.75 GS/s flash ADC is realized in 90 nm CMOS. It uses a comparator array with built-in imbalance and offset calibration to lower power consumption. The SNDR is 30.9 dB at low frequencies and gradually degrades to 28.2 dB at 2 GHz. The ADC occupies 280 um by 110 um and draws only 7.6 mA from a 1 V supply yielding an energy efficiency of 0.15 pJ/conversion step.
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