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A power reduction method for off-chip interconnects Host Publication: IEEE International Symposium on Circuits and Systems.Emerging Technologies for the 21st Century Authors: F. Devisch, J. Stiens, R. Vounckx and M. Kuijk Publisher: Presses Polytech. Univ. Romandes, Lausanne, Switzerl Publication Date: May. 2000 Number of Pages: 4 ISBN: 0-7803-5482-6
Abstract: Off-chip interconnects with a length between 5 and 20 cm can typically be modeled as lumped capacitors for operating speeds up to 50냂 MHz. These capacitors can be driven in such a way that their energy is recycled, reducing the power dissipation. This can be achieved by one or more inductors that are included at the driving side allowing energy transfer from the logic level changing interconnects to the inductors and back. Since most of the energy is recycled, the dissipation for changing logic level is reduced considerably. The method is verified first on circuits designed in 0.5 micron CMOS at Vcc=3.3 V, rendering power reduction to 48% of conventional drivers at 10 MHz operating frequency and reduction to 58% at 40 MHz
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