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High-bandwidth low-power parallel optical interconnect using imaging fiber bundles and standard CMOS detectors Host Publication: OPTOELECTRONIC INTERCONNECTS VIII Authors: C. Rooman, P. Heremans, D. Filkins, R. Windisch, G. Borghs, R. Vounckx and M. Kuijk Publication Date: Jan. 2001 Number of Pages: 6
Abstract: We present a high-bandwidth parallel optical link that operates from CMOS chip to CMOS chip, for applications like chip-to-chip, board-to-board and rack-to-rack interconnects. The optical channel is an oversampling imaging fiber bundle of 1.9 nun diameter. The light sources are a 10 X 10 two-dimensional array of high-speed, high-efficiency light-emitting diodes, designed for flip-chip mounting onto CMOS driver circuits. Detectors and receivers are integrated together in standard CMOS, as an array of 10 X 10 detector/receiver cells. These detector/receiver cells and the emitters have the same pitch of 100 mum in X and Y, such that each array fits on an area of 1 mm(2). The wavelength is 860 mum. We present the measured performance of single channels of this parallel optical link. The LEDs operate to bit rates higher than 1 Gbit/s per channel. The standard CMOS detectors operate to 600 Mbit/s in 0.6 mum CMOS technology. The data rate of the link is at present limited by the receiver, designed in 0.6 pm CMOS, to 300 Mbit/s per channel. Simulations show that a re-design in 0.18 mum should crank up this speed to over 1 Gbit/s per channel. The electrical power consumption of a complete channel is merely 4 mWatt at 300 Mbit/s for a bit error rate of less than 10(ᆠ). Each optical I/O therefore consumes on average only 2 mW. It takes up a space of merely 100 mum X 100 mum (in 0.6 mum CMOS, and scalable in newer CMOS generations). Both the power consumption and the density of the demonstrated optical link compares extremely favorably to competing electrical and optical solutions.
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