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An in-depth study of high-performing strained germanium nanowires pFETs Host Publication: 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 Authors: B. Parvais, P. Van Marcke, H. Mertens, J. Mitard, D. Jang, G. Eneman, H. Arimura, O. Richard, E. Capogreco, H. Bender, R. Ritzenthaler, A. Hikavyy, R. Loo, H. Dekkers, F. Sebaai, A. Milenin, N. Horiguchi, A. Mocuta, D. Mocuta and N. Collaert Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Oct. 2018 Number of Pages: 2
Abstract: An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at IOFF=3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology atǂ.5 VDD. The temperature dependent study of ID,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.
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