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First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers Host Publication: 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 Authors: B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, J. Franco, A. Walke, V. Deshpande, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, E. Vecchio, T. Zheng, W. Vanherle, A. Hikavyy, G. Mannaert, B. T. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, J. Boemmels, D. Mocuta and N. Collaert Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Jan. 2019
Abstract: 3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature ( T 525 C) in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.
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