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Key challenges and opportunities for 3D sequential integration Host Publication: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 Authors: B. Parvais, E. Rosseel, L. Peng, L. Teugels, A. Vandooren, J. Franco, A. Mallik, A. Hikkavyy, N. Rassoul, G. Jamieson, F. Inoue, G. Verbinnen, E. Vecchio, T. Zheng, N. Waldron, J. Boemmels, V. De Heyn, D. Mocuta and N. Collaert Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Feb. 2019
Abstract: In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of 'reliability' anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.
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