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Scaling CMOS beyond Si FinFET: An analog/RF perspective Host Publication: 48th European Solid-State Device Research Conference, ESSDERC 2018 Authors: B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. Van Liempc, A. Veloso, A. Vandooren, N. Waldron, P. Wambacq, N. Collaert and D. Verkest Publisher: Editions Frontieres, Neuily sur Seine, France Publication Date: Oct. 2018 Number of Pages: 4
Abstract: FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.
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