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A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication with 220-fs RMS Jitter Host Publication: 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 Authors: C. Tsai, F. Pepe, G. Mangraviti, Z. Zong, J. Craninckx and P. Wambacq Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Sep. 2019 Number of Pages: 4
Abstract: We present a 22.5ᆯ.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm,scaling up the PLL bandwidth for faster settling,and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO),based on transformer feedback with a tunable source-bridged capacitor,exhibits low phase noise (PN) over a wide tuning range (FoM of 낀 dBc/Hz and FoMT of 낇 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW,giving FoMRMS of 낷 dB. Its settling time improves from 780 to 45 �s with our gear-shift algorithm. For 60-GHz communication,with a frequency multiplication factor of 2.5,this PLL covers all six channel frequencies of IEEE닪.11ad and is capable of supporting 128 QAM and beyond.
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