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Conference Publication
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%0 Conference Paper %A T. Huynh Bao %A D. Yakimets %A I. Ciofi %A R. Baert %A A. Veloso %A J. Boemmels %A N. Collaert %A P. Roussel %A S. Demuynck %A P. Raghavan %A A. Mercha %A Z. Tokei %A D. Verkest %A A. Thean %A P. Wambacq %T Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies %B 44th European Solid State Device Research Conference (ESSDERC) %I IEEE %8 2014 %P 4
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