|
|
|
|
Conference Publication
|
|
|
|
|
|
|
|
|
%0 Conference Paper %A T. Huynh Bao %A S. Sakhare %A A. Mercha %A D. Verkest %A A. Thean %A P. Wambacq %T Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs %B Design-Process-Technology Co-optimization for Manufacturability X %I SPIE %8 Feb. 2016 %P 12
|
|
|
|
|
|
