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%0 Conference Paper %A P. Schuddinck %A O. Zografos %A P. Weckx %A P. Matagne %A S. Sarkar %A Y. Sherazi %A R. Baert %A D. Jang %A D. Yakimets %A B. Parvais %A D. Verkest %A A. Mocuta %T Device-, Circuit-Block-level evaluation of CFET in a 4 track library %B 39th Symposium on VLSI Technology, VLSI Technology 2019 %I Institute of Electrical and Electronics Engineers Inc %8 Jun. 2019
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