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@InProceedings{Pub_8854, author = {T. Huynh Bao, D. Yakimets, I. Ciofi, R. Baert, A. Veloso, J. Boemmels, N. Collaert, P. Roussel, S. Demuynck, P. Raghavan, A. Mercha, Z. Tokei, D. Verkest, A. Thean and P. Wambacq}, title={Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies}, booktitle = {44th European Solid State Device Research Conference (ESSDERC)}, publisher = {IEEE}, year={2014}, pages={4} }
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