|
|
B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, A. Khaled, J. Franco, A. Walke, N. Rassoul, P. Matagne, H. Debruyn, G. Jamieson, F. Inoue, E. Vecchio, T. Zheng, D. Radisic, W. Vanherle, A. Hikavyy, B. T. Chan, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, N. Waldron, V. De Heyn, J. Boemmels, N. Collaert and D. Mocuta, “Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications,” in 39th Symposium on VLSI Technology, VLSI Technology 2019, Institute of Electrical and Electronics Engineers Inc, Jun. 2019.
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