Presenter

Mr Linkun Wu - ETRO, VUB and IMEC [Email]

Abstract

A full depleted high-speed photosensitive pixel is presented, where its depletion electrostatic profile and the back bias technique are discussed. A pixel test array with 48 � 48 pixels has been demonstrated confirming a good trade-off between the speed and sensitivity. The device achieves 7 e– read noise at 80 μV/e– conversion gain. Its mean charge transfer time is estimated to 6 ns. Besides the photosensitive device, a novel in-situ storage topology for ultra-high-speed burst mode imagers is introduced to enable a low noise operation while keeping a high frame depth. Focusing on the sampling noise, system-level trade-offs of the proposed pixel architecture are discussed, showing its advantages on the noise, power, and compactness. Integrated with an AC-coupling CDS stage, the amplification is obtained by exploiting the capacitance-to-voltage relationship of a single NMOS transistor. Comprehensive noise models are developed to optimize the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 μm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank was implemented allowing a dense layout and parallel readouts. Two types of CDS amplification stages were investigated. Given a limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operating speeds up to 20 Mfps showing a good noise performance of 8.4 e–.

Short CV

Master of Science, Integrated Circuit Design, Tecnhische Universitaet Muenchen and Nanyang Technological University, 2013