Presenter

Mr Badr Malki - ETRO, Vrije Universiteit Brussel en IMEC [Email]

Abstract

Emerging wireless technologies such as 5G and Internet-of-Things (IoT) push circuit designers to implement innovative circuits with more power efficiency and bandwidth. The goal of this thesis is to investigate new circuit designs for wireless receivers which provide a better system-level power efficiency and more speed in nanoscale technologies. The core circuit is a simple transconductor playing a role of an integrator, this circuit will provide better power efficiency needed for portable wireless receivers.
In the first step, a charge-domain SAR ADC is presented which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power- hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors as the sampling capacitor for passive amplification to relax the comparator noise requirements without compromising linearity. The prototype in 40 nm low-power CMOS process consists of a variable transconductor, combined with a charge-sharing SAR ADC. This circuit achieves a high dynamic range with a low-power consumption suitable to replace the traditional VGA/ADC in traditional voltage-based baseband processing chain.
In the second step, a State-of-the-Art pipelined SAR ADC is introduced with its new complementary dynamic single-stage residue amplifier which re-uses charge typically wasted during the reset phase, and hence improves efficiency by a factor 2� in this block that often dominates the fundamental noise/power trade-off of the ADC. It is used in a 2-times interleaved coarse/fine pipelined SAR ADC. The 40 nm CMOS prototype achieves 11 ENOB at 20 MS/s while consuming 165 μW, leading to an energy per conversion step of 4 fJ/conv.-step. It maintains more than 10.8 ENOB at low input frequencies for a clock frequency up to 180 MS/s.
In the last step, a discrete-time (DT) analog baseband for software-defined radio (SDR) receivers is presented. A zero-IF baseband signal at the input of a programmable gm is converted to current, which is integrated on a 5th-order DT infinite-impulse response (IIR) low-pass filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier that integrates selected samples to implement active finite-impulse-response (FIR) filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved SAR ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype can achieve good linearity, low noise, and high dynamic range making it an attractive candidate for next generation wireless receivers.

Short CV

Master degree + Diplome d Ingenieur, Universite de Strasbourg, 2008