Presenter

Mr Nereo Markulic - ETRO, Vrije Universiteit Brussel en IMEC [Email]

Abstract

Wireless technology systems have intruded in almost every aspect of today’s communication. Technology scaling and innovation in the field of integrated circuits (ICs) nurture this wireless revolution, while the need for higher data throughput continues to grow. These trends unfold a severe challenge: in today’s over allocated spectrum, its efficient use becomes absolutely essential. In the heart of every transceiver lies a local oscillator (LO), typically implemented as a phase-locked loop (PLL). Crucial aspects of the LO synthesizer are its phase noise and spurious performance. These impose the fundamental limitation for efficient transmit and receive modes. Hence a considerable amount of energy and chip area is typically spent to minimize them. Moreover, in modern systems, the PLL is often used for phase modulation, within a polar transmit architecture. The digital signal processing in the PLL can be used to achieve this in a very controllable and flexible way.
This thesis is built around three 28 nm bulk CMOS IC prototypes, that explore and push the boundaries in the field of PLL and Polar Transmitter design. The first design explores a subsampling PLL, which originally operated as an integer-N frequency multiplier. To enable fractional synthesis, while benefiting from extremely low-noise subsampling operation, we introduce a Digital-to-Time Converter (DTC) in the phase error detection path. The DTC exploits time rather than voltage domain processing, which is a trend repeatedly seen in the recent Time-to-Digital (TDC) based PLLs. A DTC, in contrast to a classical TDC, easily reaches fine resolution that is fundamental for high performance. In the second prototype, we resolve fundamental limitations of the introduced loop, located in the linearity of the DTC, through digital background calibration. The PLL is expanded into an accurate digital phase modulator which represents the first step towards a polar transmitter. The background-calibrated DTC-based subsampling PLL operates with a -247 dB Figure-of-Merit, challenging the most advanced state-of-the art. The third and final IC introduces the Digital Subsampling Polar Transmitter (SSPTX), a new transmitter architecture that contains a digitized subsampling PLL for phase modulation and an amplitude modulating power amplifier that is placed within the PLL. The SSPTX is sensitive not only to phase errors but also to modulation amplitude. This feature enables background cancellation of phase/amplitude modulation induced distortion. The polar transmitter achieves extremely accurate performance with -41 dB EVM, 1024 QAM constellation around a 5.5 GHz carrier.

Short CV

Master of Science, University of Zagreb, 2012