Subject

Deep learning models usually have large memory requirements and require specialized processing architectures to be run efficiently, in real-time. A possible approach to alleviate this issue is to design smaller, more efficient models (e.g. deep unfolding neural networks) which have drastically less parameters and low runtime complexities, allowing them to be implemented on low-cost, low-power hardware.

Kind of work

The goal of this thesis is to study and implement an efficient deep learning model with a small memory footprint on low-power and highly-constrained devices (e.g., microcontroller).Dedicated hardware accelerators such as tensor processing units (TPUs) must also be addressed. Additionally, a video stream can be sent to the device to demonstrate the algorithm in real-time.
The project is hardware-oriented and focuses on implementing already-existing model architectures.

Framework of the Thesis

References and further reading:

Van Luong, H., Joukovsky, B., Eldar, Y. C., & Deligiannis, N. (2021, January). A deep-unfolded reference-based RPCA network for video foreground-background separation. In 2020 28th European Signal Processing Conference (EUSIPCO) (pp. 1432-1436). IEEE.

Van Luong, H., Joukovsky, B., & Deligiannis, N. (2021). Designing interpretable recurrent neural networks for video reconstruction via deep unfolding. IEEE Transactions on Image Processing, 30, 4099-4113.

Lai, L., & Suda, N. (2018, November). Enabling deep learning at the lot edge. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 1-6). IEEE.

Seshadri, K., Akin, B., Laudon, J., Narayanaswami, R., & Yazdanbakhsh, A. (2022, November). An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks. In 2022 IEEE International Symposium on Workload Characterization (IISWC) (pp. 79-91). IEEE.

Expected Student Profile

Expected student Profile:
• Knowledge of machine learning techniques.
• Interested in image processing and hardware acceleration.
• Experience of C/C++ is a plus.